Verilog !
Today,our session started with unit-2,a study on verilog language.We took up a coding as an example and covered almost all the structures required to write down a code;we came across the assignment statements-procedural and continuous, and also synchronous and Asynchronous Flip Flops.
We later on worked on the test bench briefly and had hands-on training sessions.We also learnt about the 'wire' and 'reg' data types and their functions.In our next class we are going to work more on test benches to get a clear idea about the HDL language;looking forward to it.
Today,our session started with unit-2,a study on verilog language.We took up a coding as an example and covered almost all the structures required to write down a code;we came across the assignment statements-procedural and continuous, and also synchronous and Asynchronous Flip Flops.
We later on worked on the test bench briefly and had hands-on training sessions.We also learnt about the 'wire' and 'reg' data types and their functions.In our next class we are going to work more on test benches to get a clear idea about the HDL language;looking forward to it.
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