Verilog Modelling!!!
     Today our session dealt with the modellings in verilog HDL,a theory class on verilog HDL.We learnt about the "gate level""structural level" and :behavior" modelling techniques today.We further coded verilog using case and if else conditions.We keenly worked on the testbenches for the theory taught today !.had a very interesting class ! looking forward to tomorrow's class where we are on the journey of learning the flip flops,latches and counters :)