Mock interview!!
Today we really enjoyed our session where a Mock Interview was conducted! it was really a new experience about this interview.We did learn few tips that we should remember, while attending any interview.The main thing that we learnt today was that not to give up on anything;especially "confidence".Never give up easily on anything and have Confidence in oneself.These were the key points that were noted on today's session!.

Lecture !
 Today a recorded lecture by Mr.Srikanth Jadcherla was played that dealt with the concepts of verilog .The session went on well and he gave away some examples to be worked out in our lab sessions.We finally created a group containing three members where we'll start with the project presentation soon after the Dussera holidays.Finally we are left with few more recordings to be played,followed by an interactive session with the AMD head.

Hands on Training sessions

  Today we practiced our assignment questions in verilog which made the course much more interesting.Later on, we assembled for the recording of Mr.Srikanth Jadcherla,where he recollected the concepts of verilog which gave even more basic concepts of verilog coding.! we ended up the session bit early,and still few more coding are to be completed to finish up the assignment and submit it within the dead line!

Intel..
Today we had a video conference with the INTEL manager,Mrs.Anuradha Srinivasan .!! it was an interactive session,where all our questions were answered by her.We made this session useful and all our doubts were cleared.Looking forward to another sessions with the managers of different companies.

Revision!
 We had a thorough revision on the units covered this week.! today was an interesting practical session where I deliberately coded for few circuits and wrote test benches! it was really fun looking up to the generated waves for the given codes.! We are yet to cover few more topics and assignments are given to us to be worked out.Have to keenly focus on it !! 

Verilog Modelling!!!
     Today our session dealt with the modellings in verilog HDL,a theory class on verilog HDL.We learnt about the "gate level""structural level" and :behavior" modelling techniques today.We further coded verilog using case and if else conditions.We keenly worked on the testbenches for the theory taught today !.had a very interesting class ! looking forward to tomorrow's class where we are on the journey of learning the flip flops,latches and counters :) 

Test bench
 Today we learned how to work on test bench,a bit tricky yet an interesting way to write codes :).We initially installed the iverilog software in our computers and started working on it.It was fun with the programming part.The units are partly covered and yet to finish up the portions!

Verilog !
 Today,our session started with unit-2,a study on verilog language.We took up a coding as an example and covered almost all the structures required to write down a code;we came across the assignment statements-procedural and continuous, and also synchronous and Asynchronous Flip Flops.
   We later on worked on the test bench briefly and had hands-on training sessions.We also learnt about the 'wire' and 'reg' data types and their functions.In our next class we are going to work more on test benches to get a clear idea about the HDL language;looking forward to it. 

Unit 2!
Today we discussed about the basic gates followed by the Universal gates:NAND and NOR gates. We also learnt the concepts of Universal gates and Implementation of functions using Universal gates.We keenly learnt about the implementation of  any function given using minimal number of NAND/NOR gates.Looking forward to the next session

Conference

      Today we had a Voice Conference with Mr.Jadcherla, where he have us the new concept of the internel and external Flip flops for Setup and Hold time.!! Here,we come to an end with the first unit where we'll have the tests on this unit on Saturday..

Recap..
 Today we had a recap of the Timing analysis followed by further study about the Timing Concept.Tomorrow,we'll have a video conference with the CEO,Mr.Srikanth Jadcherla,who'll explain the overview of the timing concept,once again followed by the questionnaire as per the schedule! Looking forward to the conference tomorrow,where we come to an end with the first unit.

Timing!
 Today,our IESA session dealt with the Basics concepts of timing.We started our morning sessions with a  presentation from Mr.Nagaraj Subramanyam ,Director ,ekLakshya ,VLSI  R&D company.He gave a full presentation on this course in a glad manner,where the session was very interactive!Later on,we had our Practical sessions where,we worked on MicroWind tool and practiced schematic and layouts according to today's task.We ended our session with few concepts on timing analysis,which is the last part to be covered in unit 1.Yet to learn the timing analysis in a detail manner!By the way,its Onam tomorrow! God's own country festival! Happy Onam to all..:)

Lakshya 2k14
  Today me and my mates presented a project at the KGiSL institute.It was a good experience participating again at the event;bad luck was that we couldn't participate in any other events!!may be next time,we'll plan out well and participate in all the events!!.so another day to be remembered for getting a new experience!also,our exams starts from tomorrow,hoping to do my best in all the my exams.

Lakshya

  Today I presented a paper at KGiSL institute.This is my First experience in presenting a paper and it was such a good experience to be remembered.It has relieved me off from my stage fear and has given me confidence to present anything in a crowd!the day went on well,and all my other fellow mates presented well too.Learrned few things from each presentation!.Happy that I've kept my first and the best foot forward!Ready to do,more presentations in future.Warm Thanks to the institution too,as this is my first Presentation,also they've selected my paper and happy to present it in front of the heads. 

SCHEMATICS AND LAYOUTS..
      Today we learnt much more intresting basics in our IESA class,where we had a recap on how to draw the schematics.The very Exciting part of today's class was drawing layouts!!amazed to use the software"Microwind", as i never knew that such a software existed.its was easy working on it,unless and until we know how to create schematic diagram.So,another vivid day and hoping for that we work more on this software again. 

MERRY MONDAY &Super September all the way....
  A new Sizzling SEPTEMBER has started.The Day was filled with suspense whether our daily tests would be conducted are not!finally we wrote it down well,and the day went on.In today's IESA class,we learnt the concepts of CMOS much more,in detail.Today,i had a clear view of CMOS,and really had an energy to learn more about it.
    Mr.Vamsi,our Advisor,gave a great lecture on this topic which was very interesting!hope that all my future IESA sessions go in such an enthusiasm in gaining knowledge,apart from books.So,today's class dealt with how to create a schematic diagram for any gate given,using CMOS.
   Tomorrow we are going to learn on how  to create the "Layout diagram"followed by the practical sessions.Looking forward to it!! :)